Exemplary embodiments of the present invention relate generally to a semiconductor technology, and more particularly, to a semiconductor package which is capable of selecting chips by using through-vias.
Many attempts have been made to develop a package technology which can provide improved electric performance, store large amounts of data, rapidly process the stored data and provide a slim, compact and lightweight semiconductor device. A semiconductor package technology has been proposed which improves a storage capacity and a processing speed by stacking a plurality of semiconductor chips. Various techniques for electrically coupling the stacked semiconductor chips have been proposed. One of effective techniques is to mutually connect the stacked chips using through-vias, such as through-silicon vias (TSVs), which pass through the semiconductor chips.
In a semiconductor package in which stacked semiconductor chips are electrically connected together using through-vias, the through-vias passing through the chips form electrical connection paths and thus the electrical connection paths are shortened. Due to the shortened electrical connection paths, the semiconductor package is advantageous in processing a large amount of data at a high speed. Nevertheless, since the stacked semiconductor chips are connected by the through-vias, it is difficult to select a specific chip among the stacked semiconductor chips during data processing. To select a specific chip, the stack structure of the semiconductor chips is modified to connect a signal wire and a specific chip, or the arrangement of the through-vias formed in the individual semiconductor chips is modified to form a signal path composed of through-vias connected to only a specific chip. However, in a case in which the stack structure of the chips is modified to connect a separate signal wire and a specific chip, it is structurally difficult to stack chips and configure a package. In a case in which a connection path of through-vias connected to a specific chip is separately provided, the arrangement of through-vias must be differently modified at each semiconductor chip.